• Cortex A53 : Cache policy setting
    Hi, Can somebody help me to understand how the cpu will set the cache policy to the transaction? Is it configured by any processor or descriptor? I'm enabling the caching using the SCTRL register...
  • System level Implementation of Generic Timer in Cortex A53
    Hi, Im new to ARM. Im learning generic timers in cortex a-53. I wanted to know whats the meaning of "system level implementation" of Generic Timer and "PE implementations" of the Generic Timer. How...
  • Cortex A53 Out of Order?
    Hi all, Recently I encountered a problem. During CA53 bootup stage, PC will transfer a small executable program to the target platform via USB and then give the control to that program, which will first...
  • A53 preload mechanism
    Hi, I am reading the A53 MP Core doc. My question is related to instruction preloading in aarch64. In case of a very large block of code with no function calls, I want to make sure the L1 cache...
  • About watch point debug excption on Cortex-A53
    Now we are researching watch point function on A53. We simply write a driver, hook debug exception handler aml_watchpoint_handler instead of default watch point handler. In our watch point handler...