• Cortex A53 : Cache policy setting
    Hi, Can somebody help me to understand how the cpu will set the cache policy to the transaction? Is it configured by any processor or descriptor? I'm enabling the caching using the SCTRL register...
  • shareable domain and cache policy problem
    Hi, I'm trying to find out what level is the out-most level of inner shareable domain. Is there any register to get this information? I want to know what inner shareable domain is in A53 big-LITTLE...
  • ARMv7 CortexA9 Cache Policy - No allocate ?
    I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A...
  • Cortex M4: Atomic and Cache
    Hello all, Recently I came across this issue for the cortex M4 core. We are running a freertos application which loads and stores the value of a variable. For this we are using the atomic functions...
  • Cache attribute write back/write allocate for Cortex-M4
    What is different between write back with write allocate and write with non write allocate on Cortex-M4.