• Cortex M4: Atomic and Cache
    Hello all, Recently I came across this issue for the cortex M4 core. We are running a freertos application which loads and stores the value of a variable. For this we are using the atomic functions...
  • CORTEX M4 - Output an array declared with __DATA(RAM) attribute?
    Hi to you all, I'm using an LPC4370 (in a link2 probe) to output the data acquired @ 40 MSPS using the USB CDC VCOM driver included in the LPCOPEN Libraries . I can output an array of uint32_t elements...
  • CM4: Write buffer with enabled MPU
    Hello, I have a question regarding Memory protection unit on Cortex M4 (STM32F3 MCU). This is pretty simple single core MCU without caches. I implemented MPU based on instructions in Definitive guide...
  • Cortex M4 L1 data cache policy
    I have some confusions about the difference between write back + write allocate and write back + write no allocate on Cortex CM4. As my original understanding: For write back with write allocate...
  • Cache Allocation Technology
    Hi guys, I have a question regarding "Cache allocation technology" that is present in Broadwell processors of Intel. Does ARM (aarch32/aarch64) support similar way of partitioning the LLC for a process...