• Data abort exception for unaligned access in Cortex A55
    Hi, I have written a simple assembly code in Cortex A55, which executes in EL3, 64-bit execution state. In the code, the cache and MMU is disabled which means that any memory accessed will be treated...
  • Unaligned accesses - CMSDK Example Cortex M0
    The spec mentions that the M0 will generate a Hardfault when unaligned accesses are detected. I would like to find out where is this implemented in RTL and understand it a little better. Does the...
  • cortex m7 STR fail
    I am using a STM32H753. I have an ISR that adds up some values in a 32 bit RAM location. The code adds the values and stores in a volatile RAM location. The STR instruction executes but the value is never...
  • Problem with storing data instruction STR (ASM)
    I'm a really beginner with ARM. I write a very simple program to find the sum of three values Q,R,S and store it in the memory. However it doesn't works. Someone can show me what is my mistake. Thanks...
  • Cortex-M MPU User access to privileged code
    Hi All, I currently want to make use of the MPU. I have several functions which are required to be in privileged mode and are stored in a region set as privileged-read-only, user denied, executable...