• Get current active interrupt priority
    Hi everybody, We are working on a simple priority RTC (run to completion) framework for the Cortex M3/M4. Thanks to the NVIC/BASEPRI, we got most of this functionality for free but we want to extend it...
  • What is Early write acknowledgement?
    Hi all, What is early write acknowledgement and how this attribute affects the continuous read/write performed on the peripheral/physical memory ?
  • Cortex-A9/GIC: de-activate an active interrupt
    Hi my situation: Running an OS in normal-world which due to an (user) error enters safe state with interrupts disabled. The Hypervisor enters by an FIQ (watchdog) and should reset the normal-world. No...
  • My application seems to be dropping interrupts; does returning from an interrupt clear its pending flag?
    I'm working with a Cortex M4 (Freescale's Freedom-K64F dev-board). I'm trying to write a long sequence of data to flash. The state machine for this sequence operates in the interrupt handler. This means...
  • M4 Assembly - Set Enable also enables the Clear Enable Interrupt Register
    Hi, I have some assembly for Cortex M4 (Arm 7M Thumb), I want to enable an interrupt that is connected to a push button on an STM32 F407. It works, but for some reason when I enable the set enable register...