• QSPI out of space Musca board
    Hello all, I am trying to adapt the blinky LED example of the Musca board in Keil. My new code for the secure world makes the QSPI run out of space so I removed the __USE_FLASH flag to have my code...
  • Non-secure configuration of UART1 on Arm Musca-A1
    Hi, I'm using Arm Musca-A1 and I am stuck with the configuration of UART1 to non-secure. From my understanding, to configure the peripheral to a non-secure access setting one should configure SAU and...
  • Arm Musca A1 - SRAM0 MPC Security attribute during boot
    Hi all, I am using Arm Musca-A1 in a project and I'm getting a strange behavior on the MPC connected to the internal SRAM0. During boot, I am loading some data to SRAM0 (S region). While when I access...
  • Instruction Count and Memory Access
    Hello, I was looking into the debug and trace features in the Arm Musca Board A1, which implements the Corelink SSE 200 IP (dual core Cortex M33, each with a three-stage pipeline), I came across the...
  • Cortex M33 Multicore Boot issue
    Hello there! As I am exploring the Arm Musca A1 board in a multicore scenario, some doubts emerged. When I load each core program to the FLASH memory and then boot it up, each core loads it's own code...