• Interrupt latency while STR/LDR in cortex-M3
    Hi, What is the expected behaviour on M3 when issuing STR/LDR to some remote memory (AHB) and interrupt arrive? is the interrupt being delayed although this is normal memory and this command can re...
  • Behavior for other data on a STR (ARMv7-A)
    When the following line is executed, what is the behavior with respect to the other words in the cache line? STR r1, [r0] The 4 bytes of data in r1 is written to the address in r0. But cache-lines...
  • Cortex M4 Unaligned access with STR single word access
    Hi there, I am getting a hard fault for accessing an unaligned memory address with STR single word access on a cortex M4 processor (Infineon XMC4500 F100k1024). Cortex M4 manual says that: Unaligned support...
  • Problem with storing data instruction STR (ASM)
    I'm a really beginner with ARM. I write a very simple program to find the sum of three values Q,R,S and store it in the memory. However it doesn't works. Someone can show me what is my mistake. Thanks...