• Xilinx FPGA Block ROM is used as FLASH and how to load the program in to this?
    Hi, I am using the SoC design from Desgn Start - Eval version for Cortex-M0 with only modification of using Xilinx Block ROM as the Memory for FLASH ROM as well as for RAM. And my goal is to load...
  • Where can I find the device-specific JTAG instructions for Cortex-M3?
    I'm trying to communicate with a Cortex-M3 based microcontroller (LPC1769) through JTAG. I already have the hardware required, and have managed to get an example program to work, but to progress further...
  • Cortex-M0 DesignStart R2
    For the last weeks, I have been trying to get this new version to work. I did the same as with the previous version and now it is running on the Xilinx Nexys4. However, honestly I do not have any idea...
  • SWD: Cannot connect to MEM-AP on Cortex-M0 Designstart Eval
    I am evaluating the SWD-Port of the Cortex-M0 Designstart using the obfuscated component of the Eval distribution AT510-MN-80001-r2p0-00rel in a Modelsim Simulation. For that purpose I composed a minimal...
  • External BRAM as I/D memory for Cortex-M1 DesignStart package for Xilinx FPGAs
    Hi, I'd like to try and use external BRAM as the I/D memory for the Cortex-M1 DesignStart package for Xilinx FPGAs. The reference examples for Arty boards use the internal TCMs. I've built a design...