• Cortex M7 cache ECC error
    Hi, I'm currently working on STM32H7 which run a cortex M7. I'm trying to figure out how an ECC error upon a look up in the instruction or data cache is reported to the core. The only mention I've...
  • Cortex M7 SPI Interface Register Base Address
    Hello, I am trying to use the SPI interface on the Teensy 4.0 board which has a Cortex M7. I found the registers and there offsets in the RM0444 Reference Manual but can't find the Base Address of...
  • Cortex-M7 load instruction latency and pairing
    Hello, What is the latency for the LDR instruction when the result is used for integer arithmetic operations (for example DSP MAC instructions)? Also, can 64-bit loads (LDRD) be paired with another instruction...
  • Cortex-M7 Launches: Embedded, IoT and Wearables
    Cortex-M7 Launches,you can read a detailed introduction from AnandTech. AnandTech | Cortex-M7 Launches: Embedded, IoT and Wearables And you can also find the information from ARM official website: Cortex...
  • Why use Cortex-M7 dual-redundant core?
    Cortex-M7 has an parameter named "LOCKSTEP" which specifies whether the implementation is a dual-redundant core and uses lock-step. My question is: why do I need to implement the dual-redundant core...