• L2 cache error injection for instructions and Prefetch Abort
    Hello, I am using an ARM dual core Cortex A9 CPU as part of our satellite computer SoC, and I am trying to inject errors in the different cache levels of the CPU. In particular I am trying to...
  • L2 cache error injection and Prefetch Abort
    Hello, I am using an ARM dual core Cortex A9 as part of our satellite computer SoC, and I am now trying to inject errors in the different cache levels of the CPU. In particular I am trying to trigger...
  • Snake robot with ARM Cortex-M4 processor
    I want to design an snake robot with ARM Cortex-M4 processor can u help how to start? please help me.
  • Cortex-M pipeline, relationship prefetch and decode stages
    Hi ARM specialists, I have a question about Cortex-M series pipeline behavior. According to the page 15 of "ARM Cortex-M Programming Guide to Memory Barrier Instructions Application Note 321", it is described...
  • D-side prefetch Cortex-A8
    Hi at all! At the moment I implement the initial routines and cache-handling for Cortex-A8. All the implementation is according the Boot-Code example in Cortex-A8 Programmers Guide on page 13-4. Now I...