• Difference between revisions
    Hello, I'm very new at the community, I want to start working with the ARM cortex A15, while looking for the datasheet, I got the page ARM Information Center , where I found a LOT of information about...
  • CPUACTLR_EL1 and S3_1_C15_C2_0 in Cortex-A57 TRM
    hi, experts:  In Cortex-A57 TRM chapter 4.3.66 : It defines CPUACTLR_EL1 register, but this register name is not CPUACTLR_EL1. Its name is S3_1_C15_C2_0. Why? best wishes, hi
  • What ARMv8.x revision Cortex-A35 is?
    Hi, ARMv8-A specification mentions revisions and options. I cannot find Cortex-A35 adheres to which exact version: ARMv8.1, 8.2, 8.3? I want to know which of the extensions described in the generic...
  • Does ARM-7 also support GelobalPlatform specifications?
    Our company needs to check proof of concept to change the Trust Zone from Qualcomm based on 8974 which based on ARM-7 to Google Trust Zone Operating System. Does somebody know if is possible? Which...
  • Normal/Non-shareable/Non-cacheable memory note on Cortex-A5 TRM
    Does anyone know what means "Does not access L1 caches." note in the "Treatment of memory attributes" table from [1] for Normal/Non-shareable/Non-cacheable memory for Cortex-A5? Thank you! [1] infocenter...