• ARM PMU access DRAM Event
    Hi, accorting to the reference manual of cortex A7 https://static.docs.arm.com/ddi0464/f/DDI0464.pdf pagina 243, what event number i neet to select to count all the DRAM access (read / write)?
  • about cortex-A72
    hello guys, can you tell me the number of execution units in Cortex-A72 and the number of clock cycles it takes per instruction? Thanks in advance
  • A72 Invalidate dirty cache line (DC IVAC)
    The A53 TRM says that when you invalidate a dirty cache line (DC IVAC), then a clean is automatically performed before the invalidate. Does the A72 have the same behavior? Is it possible to invalidate...
  • Cache ECC in Cortex-R5 & Event bus
    Hi everybody, I am using a Cortex-R5 embedded in a TMS570LC4357, and I am wondering to use the cache configuration as "Do not generate Aborts, force write through, enable hardware recovery". As far...
  • Cortex-A72 and Cortex-A5x series boards
    Hi Experts, Is there any sample development boards available on Cortex-A72/5x series ? Regards, Techguyz