• DRAM address mapping on a Cortex-A72 ARMv8
    HI Everyone, I need help about DRAM address mapping on a Cortex A-72 especially my question is : given two physical memory addresses how can i know if they are in the same DIMM, Rank and Bank ? is there...
  • Address decoding in AXI4 interconnect
    Hi, anybody explain how data  is routed in interconnect? As stated in AXI4 spec, only start address issued from master,then how it is done in case of burst transaction? Please Explain how this is done...
  • ARM PMU access DRAM Event
    Hi, accorting to the reference manual of cortex A7 https://static.docs.arm.com/ddi0464/f/DDI0464.pdf pagina 243, what event number i neet to select to count all the DRAM access (read / write)?
  • Juno DRAM device model
    Is there any pointer or an ARM-internal contact to ask about the DRAM device used in Juno board? It is 32-bit width, so simply I wonder if it is composed of 4 of 8-bit device or 8 of 4-bit device.
  • initialisation of DRAM ECC with Cortex A9 CPU
    Hello, I would like to find the most optimal method to initialize the DRAM ECC of my Xilinx Zynq7000 SoC. Zynq7000 SoC comprises a dual core Cortex A9 CPU with L1 data and and L1 instruction caches...