• MSP & PSP - 'Using it All'
    As I understand it, if, when my system boots and I switch to using PSP (process stack pointer) and allow the CPU to handle exceptions using MSP? Have I got that the right way around? The reason is that...
  • M0+ Stack Pointer (PSP/MSP) Clarification
    Background I'm working part-time on a Cortex M0+ based SoC converting a very processor-intensive section of C++ code (inner-loop executed 10s of 1000s of times a second & compiles to over 400 instructions...
  • The reason why the exception frame forms on PSP?
    Hello experts, I would like to ask the reason why the exception frame forms on PSP in the Cortex-M architecture. My understanding is that MSP (Main Stack Pointer) is the interrupt stack pointer and PSP...
  • PSP Stack Pointer, what memory address does it point to?
    In the ARM Cortex M4, If the PSP stack pointer is configured, what address space does it point to?  Is it the same address space as the MSP (main stack pointer)? Or do we create a new and separate stack...
  • Use-cases of AXI3 unaligned transfers
    Hi all, I cannot think of a good usecase of unaligned transfers in AXI3. - For unaligned write, a master can anyway use aligned write + write strobes. - For unaligned read, a master can use aligned...