• Cortex-A9 core registers
    In RTL code of A9mp platform provided by ARM, I see that almost all registers are renamed and are out of order(There are registers named R0-R55). This make it quite difficult for me to debug some problems...
  • cortex A9 multi-core
    I'm learning cortex-a9 on freescale imx6 platform. How to start multi-core? And how to communicate between cores? I'm confused.
  • Cortex A9 single core
    From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions: SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still...
  • Cortex-A9 TLB lockdown
    Hello, expert. I tried to implement TLB lockdown in Cortex-A9. Cortex-A8 and ARM1136JF RFP offer detailed TLB lockdown method but cortex-A9 RFP doesn't offer it. I tried TLB lockdown following Cortex...
  • What is the lowest frequency I can run ARM Cortex-A9 Processor ?
    What is the lowest frequency I can run Cortex-A9 Processor ?