• How to set up stage-2 translation table
    Hi, I am trying to enable stage-2 translation for Armv8 aarch32, cortex-a53. If I set HCR.VM=1(enable stage-2 translation) it will crash. I suspect it does not set up stage-2 translation table. But...
  • Difference between ARMv8 Data Abort exception subtypes "Not in translation table" and "Translation table fault at level"?
    I've gotten virtual memory working on ARMv8 after crafting the page tables. Oddly, _most_ of my translations are working (identity mapped) save for Flash which sits at physical address zero. I use a single...
  • Synchronization of caches on ARMv8
    Hello, I have a question regarding the synchronization of caches on ARMv8 on Multi-Core. Let's assume that we have 2 cores that are running in parallel, and both has L1 Cache with line size = 64 Bytes...
  • ARMv8 PMU access
    Hey guys, I'm running a sw in a multicore ARMv8 system and I'd like to know a bit more about the PMU component. There is a PMU per CPU, right? Is it possible from one CPU to access the other CPU...