• Cortex-R4: Need a explanation for dual-issue restriction
    Hello, The following table is extracted from the Cortex-R4 whitepaper: Could someone help me to explain that question: My concern is that Cortex-R4 can take MOV as first instruction, ADD as second instruction...
  • Question about a code snippet on ARM, Thumb state change
    Hi, I find the following code snippet online on ARM state change. Although that whole material looks solid, the second line in the blue code below is puzzling. add R1,PC,#1 ;Load address of SUB_BRANCH...
  • where can I find the detailed explanation of ARM PMU events?
    Two questions: 1. Where can I find the detailed explanation of ARM PMU events? 2. How to know the stall cycles for e.g. icache miss etc.? Thanks.
  • Explanation of cycles on pre and post index-addressing in case of Load and Store instructions.
    Hello to all, I am working on Cortex-M4 and in order to implement the load and store instructions, I have chosen the pre and post-index addressing and the memory arrangement is little endian. Therefore...
  • ARM assembly
    I have to write an assembly code in arm (cortex A-8) ,which assigns a value passed by the user(pass by value) to a particular general purpose register(for example r0). my function looks like this ...