• initialisation of DRAM ECC with Cortex A9 CPU
    Hello, I would like to find the most optimal method to initialize the DRAM ECC of my Xilinx Zynq7000 SoC. Zynq7000 SoC comprises a dual core Cortex A9 CPU with L1 data and and L1 instruction caches...
  • Cache ECC in Cortex-R5 & Event bus
    Hi everybody, I am using a Cortex-R5 embedded in a TMS570LC4357, and I am wondering to use the cache configuration as "Do not generate Aborts, force write through, enable hardware recovery". As far...
  • Why Cortex-R5 Bus-ECC documentation different from Cortex-R7
    Hello Support, In the Cortex-R5 TRM [Section 9.1.1 -- Bus ECC -- Chapter is  Level Two Interface] I see the following statement: " It is possible that fatal, that is double-bit, ECC errors might cause...
  • On a watchpoint synchronous data abort, how do I determine the data address?
    I have code that sets up watchpoints, and handles them in the data abort handler. However, I would like to be able to compute the data address. I have the PC value, but I haven't been able to find a source...
  • Data Abort on read, although write can be executed without any abort.
    I am a begginer to arm and I have a problem with understanding Data Abort that I get when reading from memory (ATCM) when I read from atcm. next pc jumps to 0x10, so Its Data Abort. However, If I...