• Systick precision
    Hi all, To prove that my code was configuring the systick counter correctly, I did a small test. To measure the interval length between each SysTick interrupt handler I used SWV in combination with...
  • ARM926EJ-S, Can a STMIA result in four single accesses instead of a burst?
    Hello Community, I have a question regarding the STMIA instruction in an ARM926EJ-S. We build a SOC with this core and one of our own modules connected to the DATA-AHB has a bug. One workaround for this...
  • Precise Memory Error
    Note: This was originally posted on 3rd August 2010 at http://forums.arm.com I am working with a Cortex-m3 using assembler and am getting "precise memory errors".  The manuals refer to this fault a lot...
  • Cortex A9 single core
    From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions: SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still...
  • PMU in arm11 results
    Hi, I am programming raspbery pi model b ARM1176 bare metal (in assembly and c). I need to calculate the clock cycles used to execute an assembly code. I am using the following code for PMU counter: ...