• Questions regarding NEON
    Hi, for a project regarding Digital Signal Processing on ARM SoCs i'm currently gathering some information about the ARM NEON engine and would need some clarification if my assumptions are correct. I...
  • Regarding mismatched memory attributes and cacheability
    As described in ARM ARM (ARMv7), mismatched memory attributes for mapping a physical region would happen when either/all of the memory type, shareability or cacheability of aliases differ My question...
  • Beginers questions regarding ARM development.
    I am just starting out developing with ARM and am really enjoying learning about these processors. I have a few questions that have been on my mind as a newbie that I'm hoping some people can answer....
  • Regarding Visibility of Multi Master ACE-Lite System
    So in my system I intend to use 3 ACE-Lite Masters. As per spec the cache of ACE-Lite masters cant be accessed by ACE masters but cache of ACE masters can be used in broadcast cache maintenance operation...
  • Hi, regarding AXI wrte strobe functionality...
    I'm trying to understand the write strobe functionality for a 128bit bus width, burst type FIXED. Case scenario: AXI bus width 128bit. awlen    = 3 (4 write transfers) awsize  = 2 (32bit per each transfer...