• Question about ARM exception and CPSR status
    Hi , for ARMv7-A15, when an exception is issued, such like a "smc #0" instruction in supervisor mode, ARM hardware will jump into the vector and CPSR will be changed in monitor mode. my question is, what...
  • BCC vs BNE
    To detect negative numbers why do programming use BCC (check carry bit ) instead of BNE ( check N bit , which is obviously more straightforward ) ?
  • How to get/download core_cr5.h
    How to get/download core_cr5.h
  • ARM Cortex A8 - if IRQ interrupts are disabled in CPSR register While the processor is executing, system results in data abort. What might be the reason to trigger data abort
    ARM Cortex A8 - if IRQ interrupts are disabled in CPSR register While the processor is executing, system results in data abort. What might be the reason to trigger data abort cpsid i;          // instruction...
  • Debug using gdb debugger, how to get the exception level?
    I'm debugging the ARM Cortex A53 on the QEMU emulator using gdb debugger, any idea on how to get what exception level I'm running on (EL3/2/1/0) ?