• How to generate an address size fault?
    Hi experts, I am new in ARM and I am trying to understand the theory behind address translation in order to generate an address size fault at different levels. I know that during the process from virtual...
  • Invalid state usage fault( INVSTATE ) for arm instruction
    Hi, We tried to execute a small assembly instruction function in .asm file for M7 core controller in GHS. But it initiated a hard fault exception with INVSTATE (Invalid state usage fault) bit is set...
  • sp register minus fault in stp instruction
    summary: sp (0000000012108d90) - 48 = 0x 4 000000012108d60 when exec stp instruction (62 bit become 1). Could anyone help to explain why this happen? Thanks. the details in below: We get a level...
  • Hard Faults and MemManage Faults in Cortex m3/m4
    I wrote a simple program, where I am writing to an illegal memory location. Writing in an illegal Memory location generates a MemManage fault. And if MemManage is not enabled, HardFault in generated....
  • Unhandled fault: alignment fault (0x92000061) at 0x00000000fff0f729
    Hi, I have an arm cortex A-57 machine that is running 3.16 linux kernel (64bit) compiled using gcc-linaro-aarch64_be-linux-gnu-4.9-2014.09_linux toolchain. My application (32bit) is accessing a member...