• The exact definition of outer and inner in ARMv7
    Hello, I'm reading ARMv7 architecture reference manual and there are the following keywords: outer cacheable inner cacheable outer sharable inner sharable It looks like that outer/inner...
  • Inner/Outer share ability in Cortex R52
    I am trying to configure memory attribute for cortex R52 in our SOC which is having integrated L1 I/D Cache and no coherent agent.and having system RAM. system is having two clusters with two cores...
  • why inner attribute is affected by outer configuration?
    Hi expert: I am configuring a CortexA15 system. In the LPAE page table entry, SH[1:0] is configured as 11, so this is a Inner Shareable field. Then I need to set MAIR0.attr0 which is used by stage 1...
  • How to set inner of outer shareability on page table entry WITHOUT TEX remap??
    At first, sorry to my fool English. I want to know how to set to inner or outer shareable attribute on page table entry using TEX, C, B and  S bit (without TEX remap). I knew if i use TEX remap, the PRRR...
  • Cortex-A9: Eviction of dirty line from the region marked as Only "Inner Cacheable" from L1 cache - will if be allocated into L2?
    Hello, Consider following scenario: A 4 KB page starting @0x80000000 is marked as Normal Memory, Inner Cacheable, write-back, non-shareable, non-outer cacheable, L2 is inclusive cache. Now, the s/w writes...