• Lock-Step mode execution on Cortex-R5
    Dear Forum, Could some one please elaborate on , 1. what is Lock-Step Mode ? 2. What is the General HW configuration required ? 3. How to make a program/application executable in Lock-Step mode ? - In...
  • Cortex-R52 data cache content
    Hi everyone, Is there a way to read the data cache content? I'm using Xilinx SoC ZCU102 evaluation board. Thanks
  • How to test " Lock-Step " is working on Cortex-R5 ?
    Dear Forum, How to test " Lock-Step " is working on Cortex-R5? Please provide inputs on Testing this feature. Thanks, Ravinder Are
  • Hypervisor for Arm Cortex A9
    Hello all, I am currently working on a project with a SoC Zynq development board (Cora Z7) that has two Arm A9 processors. I would like to use a hypervisor in order to partition the software. I have...
  • ARM Cortex-R5 based Lock-step feature demonstration real time application?
    Dear Arm community, is there any real-time application to demonstrate the R5-lock step feature. other than Error injection in to the test register ? Thanks, Ravinder Are