• PMU Register description is not clear in Arm Cortex -R52 Processor Revision: r1p1
    Hi , I am NXP working for functional validation group and writing PMU API but facing issue for detailed description of many of the PMU registers . I am referring to "Arm® Cortex®-R52 Processor Revision...
  • How to calculate the CPI for ARM Cortex-R4
    How to compute the Clock cycles per instruction for arm cortex R4 ? is it straight forward as, CPI = clock cycle counter (computed using PMU) / Number of instruction executed (computed using PMU) or CPI...
  • Which instruction format does Cortex-R support,encoding A1 orA2?
    I see it support encoding T2 for Thumb-2 instruction set.But which instruction format does Cortex-R support for ARM instruction,encoding A1 orA2?
  • reference source code to verify the Cortex-R52
    Hi experts, I'm studying and doing some research the Cortex-R52, I plan to run a RTOS on Cortex-R52, however, I can not find the reference. I need to verify the new feature on Cortex-R52, and can...
  • Is that possible for Cortex-R5's dual-core to handle interrupt during lock-step mode?
    As I know, Cortex-R5MP supports lock-step mode and every output from two cores will be compared in this mode. I'm curious about the handling of Interrupt Service Routine during the lock-step mode. ...