• Trace decompressor: Are barrier instructions and synchronization primitives really waypoints?
    Dear all, System: Altera Cyclone V with ARM Cortex-A9 dual-core MPU. CoreSight PFT 1.0 I am currently developing a trace decompressor. I wrote a function that parses the program image in order to...
  • Synchronisation Primitives and Exclusive Monitors
    Later versions of the ARM architecture, using the LDREX/STREX instruction family, use "Exclusive Monitors" for inter-processor synchronisation of Shared Memory. How are these Monitors ("Local" amd " Global...
  • Break Points and Watch Points
    Greetings,                Sir,i am working on SWD, after  Research on Break Point & Watch Point i found One Thing That There are Some Comparators will Do These Things but I am not Very Sure That How These...
  • Is ARMv7-M3 thumb instructions compatible to ARMv7-A thumb?
    Hello guys, I am trying to verify some features of ARMv7-M3 in a software simulator platform for ARM. But this simulator only support ARMv7-A ISA. Is ARMv7-M3 instructions compatible to ARMv7-A, especially...
  • Present program counter address
    Good day, I want to refresh and (or) update my knowledge on ARMv7. Is it true for ARMv7-M that when CPU starts execute one instruction, PC value has already been updated/is being updated in parallel...