• Barriers in in-order cores like cortex-A53, A7
    Hi experts! As you know, power efficient arm like cortexA7, A53 has in-order pipleline. However as far as I understanding, Barriers like dmb, dsb, isb are related with out-of-order memory access. But...
  • Why use Cortex-M7 dual-redundant core?
    Cortex-M7 has an parameter named "LOCKSTEP" which specifies whether the implementation is a dual-redundant core and uses lock-step. My question is: why do I need to implement the dual-redundant core...
  • Cortex-A7 4 Cores Boot
    Hi , I am working on Arm for the first time . I am trying to implement a scenario to boot 4 cores parallel . I have few queries here      --> Reset lifting procedure for 4 cores ? how exactly they should...
  • Can we run the Cortex-A53 cores at different clock speeds ?
    Dear ARM Group, Can we run the A53 cores at different clock speeds? if YES,  How does it effect the complete A53 (L2 cache etc) and system? if NO,  What are the constraints ? could you please give a detailed...
  • ARM Cortex-A53 System Register
    Hello, I wanted to check the value of following interrupt related registers i.e. ICC_IAR1_EL1 ICC_EOIR1_EL1 I'm able to find the ICC_IAR1_EL1 inside the CORTEXA53 hierarchy. But NOT able to...