• FPB BreakPoint(without Debugger)
    Hello, My App (cortex m4) needs to set up a breakpoint directly from code, in order to jump to an interrupt when an instruction from a certain address is fetched. This without using a debugger. I searched...
  • Does ARMv8-A has VC_CORERESET or something similar?
    Hi All. Does ARMv8-A has something similar to VC_CORERESET bit in Debug Exception and Monitor Control Register of ARMv8-M ; which enables halt on reset vector on warm reset? Or is there any other method...
  • Cortex-M0+ hangs on return
    During debugging the Cortex-M0+ (ATSAMR21G18) all of a sudden hangs. Stack looks fine. LR contains the correct return address (odd), which based on the BX instruction description ( http://www.keil.com...
  • Hard fault : Cortex M0+ platform.
    Hello, Micro-Controller platform: STM32L0x1 Environment: Bare-Metal (No OS) Brief description of the problem: From interrupt context, we are trying to copy information received to EEPROM. Soon...
  • Does E0PD mechanism provide Meltdown mitigation?
    ARMv8.5 introduces E0PD mechanism that changes faults timing (as declared in spec). Other side, there is a patch to Linux kernel that disables KPTI if cores support E0PD. From description in spec it's...