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    If two AXI masters are sending transactions with same ID, how to send response correctly to the respective masters
  • Hardfault issue
    I am facing a hardfault issue . I have debugged from software perspective . My observation is I am trying to reproduce this issue n many devices but I am facing this issue in 2 out of 10 boards and hence...
  • STM32H7 CAN FD issues
    Hi everyone, I find myself working on a board with this microcontroller and I just have to get the CAN bus working. I have never done any programming with neither CAN or this micro. The issue I...
  • SWD issue in Cortex-m0
    We are using Cortex-M0 DesignStart Pro to design MCU. When we use SWD to download grogram to flash in FPGA(Cortex_m0 mcu inside), we cannot to connect keil with FPGA, and Keil shows:" Could not stop Cortex...
  • Cortex-A8 debug issues
    Hi expert Since I debug AM3354(Cortex-A8 Core), I want to enable IRQ, so I write the assembler code: IntrEnableIrq MRS R0, CPSR ; Pickup current CPSR BIC R0, R0, #0X80 ; Clear interrupt lockout...