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    I'm struggling to track down a problem here. It appears to be that the stmdb instruction isn't pushing all of the requested registers, and when the corresponding ldmia.w instruction executes, it pops...
  • Present program counter address
    Good day, I want to refresh and (or) update my knowledge on ARMv7. Is it true for ARMv7-M that when CPU starts execute one instruction, PC value has already been updated/is being updated in parallel...
  • two’s complement
    How to load the two’s complement representation of -1 into Register 3 using one instruction? i am working on ARM7 and NXP processor.
  • Debug using gdb debugger, how to get the exception level?
    I'm debugging the ARM Cortex A53 on the QEMU emulator using gdb debugger, any idea on how to get what exception level I'm running on (EL3/2/1/0) ?
  • Does Cortex-M0+ has a flash patch mechanism similar to the FPB function of Cortex-M4?
    Hello, As shown in title, does cortex-m0+ has flash patch and break point(FPB) function similar to cortex-m4, which will facilitate the upgrading of ROM code in the form of hardware. Thanks