• Speculative execution/loads on Cortex-A5
    Hello. I just found some information about speculative execution and speculative loads/cache line-fills on some ARM processors. Unfortunately I wasn't able to find if any of these present on Cortex-A5...
  • Speculative Branching.
    Hi, I am new to ARM Cortex M3 Microprocessors. Can somebody please explain me the speculative branching in layman terms. Thanks in advance.
  • Is ARMv7-M3 thumb instructions compatible to ARMv7-A thumb?
    Hello guys, I am trying to verify some features of ARMv7-M3 in a software simulator platform for ARM. But this simulator only support ARMv7-A ISA. Is ARMv7-M3 instructions compatible to ARMv7-A, especially...
  • unaligned data fetch in Cortexa9
    I have a question related to data fetch, when on gdb debugger I do an address read say as: X 0x81000000 Then it will fetch 64 bits as you told in reference to Cortex A9 If further I do X 0x81000004 Will...
  • ARMv7-M: Question about syn/asynchronous exception?
    Hi all, I have little experience with bare metal programming at STM32 series and currently studying exception behavior in "ARMv-7m Architecture Reference Manual" . I'm confused about syn/asynchronous...