• Regarding ADFSR and AIFSR in ARM Cortex-A9 MPcore
    Hello all, I was debugging an imprecise external abort in one of our product based on i.MX6q and came across a register - Auxiliary Data Fault Status Register readable and writable by the following instructions...
  • Address memory of the next instruction in A9 MPCore
    Hi all; I need to know the address that contains the next instruction to be executed in a A9 MPCore. That is, I need to read the Program Counter (PC). Where is the program counter? I can't find it...
  • which register are dedicated for each MPCore in ARMv8-A architecture?
    Hi Expert, I'm a beginner to ARMv8-A architecture MPcore and now studying A35 MPCore processor documents for low-level software developing. One question, when I read DDI0487C_a_armv8_arm and DEN0024A_v8_architecture_PG...
  • Cortex-A15 MPCore: How to Enable Monitor Debug Mode
    Hi experts, I want to enable monitor debug mode for Cortex-A15 MPCore. I tried modifying DSCR[15] bit but watchpoint event still won't generate exception/abort. Core was in no-debug mode before modifying...
  • What is the difference between PoC and PoU for Cortex-A7 MPCore?
    hi, experts: ARM ARM manual introduces a concept PoC and PoU for cache maintanance operations. Based on Cortex-A7 MPCore TRM and ARM ARM manual, i got below conclusion: 1. PoC points to external DRAM...