• Cortex-A9 TLB lockdown
    Hello, expert. I tried to implement TLB lockdown in Cortex-A9. Cortex-A8 and ARM1136JF RFP offer detailed TLB lockdown method but cortex-A9 RFP doesn't offer it. I tried TLB lockdown following Cortex...
  • Penalty estimate of TLB miss or table walk in armv8
    Hello! Is there are rough estimate oh what would be the penalty for each tlb miss or table walk for different table levels? And what are the factors that can determine the deviation between each measurement...
  • AArch64 TLB maintenance requirements
    Hello all, I want to improve VM operation in AArch64 port of FreeBSD but I stuck on following problem. The FreeBSD VM subsystem is capable to map various *kernel* objects by using superpage (higher order...
  • Bus error while executing ARMv8 TLB instruction
    Hi, I am facing "Bus error on memory operation" while executing below instruction while invalidating and flushing the TLB. I am not able to understand what is the reason for "Bus error" as it is a TLB...
  • L2 TLB internal memory access through RAMINDEX
    Hi Experts, I need to access L2 TLB internal memory for A76 core (Section A6.6 of Cortex A76 TRM) . I was searching for an example code and found this for A57 core: LDR X0, =0x0000000001000D80...