• AXI problem
    Hi All I have few questions about axi Q1: is it possible that WVALID , WREADY and BVALID assert at the same cycle? Q2: what is different between out of order and data interleaving ? Q3: is it possible...
  • axi ordering
    Hi the master is connected to axi-interconnect and two slaves(A and B) are connected to axi-interconnect. The master send a write transcation(AA) to slave A and then send a write transcation(BB) to slave...
  • TZC380: AXI ID and AID_WIDTH
    Hi everyone, I am trying to configure a TZASC (TZC380) in my secure kernel to prevent Linux and some DMA to mess with the secure part of DRAM. In the documentation, the FAIL ID register holds the identifier...
  • AXI SLAVE PERIPHERAL
    Hi everyone! Please help me.. i have a project with a custom axi slave design that implements multiple memory ranges 256 words each . A master ( my processor in figure) can write burst data to the example...
  • AMBA3 AXI - Exclusive access
    1/ What will happen when a master performs 2 exclusive read with 2 different transaction ID to the sam an address location?? Example: Master0 (M0) issue 2 exclusive read with 2 different transaction ID...