• ARM1136: why the mismatch between cache stalls and cache misses ??
    Something weird when I count both Instruction Cache Miss event and event 0x1 (viz. “Stall because instruction buffer cannot deliver an instruction. This could indicate an Instruction Cache miss or an...
  • PMU (Performance monitor Unit)
    Hi, How can I use PMU(Performance Monitor Unit) in ARM11 to calculate execution clock cycles of an assembly code. I am using raspberry pi Model B. I am programming it in assembly language (running assembly...
  • Page Colouring on ARMv6 (and a bit on ARMv7)
    Page colouring is a technique for allocating pages for an MMU such that the pages exist in the cache in a particular order. The technique is sometimes used as an optimization (and is not specific to...
  • cache invalidation
    Hi, If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written...
  • Which ARMv8 register controls cache partitioning
    Hi ARM folks, Which register controls the cache partitioning behavior on ARMv8 chips? My group is working with a Cavium ThunderX, and we're trying to experiment with different cache partitioning...