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    Hi Experts, I'm researching Cortex-A53 cache. Can Cortex-a53 l2cache be enable/disable independently? Is it possible to only enable l1 cache and disable l2cache? Does cortex-a53 support l2cache...
  • Protection control
    Dear Team , Currently i am Developing and verifying AHB 5 Protocol. I am not able to understand HPROT signal and its behavior. Please help to get clarity on this signal and its behavior.
  • Unable to Download Code to Controller
    Hello All, We have custom PCB having ATSAME54P20A microcontroller. Suddenly today I started getting CPU Status - LOCKUP error and I am unable to download the code to the microcontroller. Before, that...
  • Control access to L2 cache
    Hi, I want to use a dual core with shared L2 cache. On Core0 I want to run Linux and on Core1 I want to run Bare - Metal. Is it possible to control the L2 cache access in case both Cores want to access...
  • Programmable Interrupt Controllers: A New Architecture
    A programmable interrupt controller is an IP block that collates many sources of interrupt one one or more CPU lines, as well as submitting a level of priority to the interrupt outputs. It’s fair to...