• Prefetch Abort in Cortex M processors
    Hi, We are currently working with Cortex M4 processor and previously we worked with Cortex R5 processor. As part of our project requirement, we need to detect "prefetch abort" exception and to identify...
  • D-side prefetch Cortex-A8
    Hi at all! At the moment I implement the initial routines and cache-handling for Cortex-A8. All the implementation is according the Boot-Code example in Cortex-A8 Programmers Guide on page 13-4. Now I...
  • Disable data prefetching in a Cortex-A53 running Android
    Dear Experts, I would like to disable the data prefetching engines of the L1 and L2 caches on a MediaTek-X20 board which includes a quad Cortex-A53 cluster and runs Android. I have tried to include...
  • Cortex-M pipeline, relationship prefetch and decode stages
    Hi ARM specialists, I have a question about Cortex-M series pipeline behavior. According to the page 15 of "ARM Cortex-M Programming Guide to Memory Barrier Instructions Application Note 321", it is described...
  • AXI 4 burst boundary
    Hi All, I searched alot that why AXI 4 is having 4k boundary , but I didn't get the answer . Can any one explain deeply for this ???