• Cache ECC in Cortex-R5 & Event bus
    Hi everybody, I am using a Cortex-R5 embedded in a TMS570LC4357, and I am wondering to use the cache configuration as "Do not generate Aborts, force write through, enable hardware recovery". As far...
  • instructions fetch
    Hello, when I use stm32f103xx, I am confused of one of the boot modes it supported. One of the boot modes is booting from embedded SRAM while the I-BUS of Cortex-M3 is connected to FLASH only . When boots...
  • Hypervisor Mode to System Mode in R52 cortex
    Hi Expert, I am using processor with R52 Arm cortex and I need to change hypervisor mode to system mode during run time i.e EL2 to EL1.Is there any instruction to change this? Thanks In Advance...
  • Lock-Step mode execution on Cortex-R5
    Dear Forum, Could some one please elaborate on , 1. what is Lock-Step Mode ? 2. What is the General HW configuration required ? 3. How to make a program/application executable in Lock-Step mode ? - In...
  • How to test " Lock-Step " is working on Cortex-R5 ?
    Dear Forum, How to test " Lock-Step " is working on Cortex-R5? Please provide inputs on Testing this feature. Thanks, Ravinder Are