• Cortex-M RTOS related exceptions and concepts
    Hello, Recently, I came back to digging into RTOS working principles at the lowest level on Cortex-M family processors. I understand the concept of SysTick (or other time base), SVC and PendSV as RTOS...
  • Present program counter address
    Good day, I want to refresh and (or) update my knowledge on ARMv7. Is it true for ARMv7-M that when CPU starts execute one instruction, PC value has already been updated/is being updated in parallel...
  • two’s complement
    How to load the two’s complement representation of -1 into Register 3 using one instruction? i am working on ARM7 and NXP processor.
  • Hard Fault in cortex m4
    Hello All, Good Morning! I am working on Cortex m4. I have read following about hard fault , "Bus Fault: detects memory access errors on instruction fetch, data read/write, interrupt vector fetch, and...
  • Endian in Cortex-M4
    Hello to all, I am working on ARM Cortex-M4. Since it has 32-bit address bus, therefore I assumed that each 32-bit instruction will be allocated a physical address location in the Flash. But while reading...