• Verilog bus functional models for AHB master simulation
    I see in the documentation site that ARM offers up some bus functional models to simulate both a 32 and a 64 bit AHB bus master in Verilog RTL. Where do I find these models, and what is the cost? I am...
  • How to implement to write firmware by JTAG within CM3 design kit?
    Dear all, I believe that you know such as STM32F103 cpu series support firmware program function by using JTAG with JTAG debugger of keil MDK. So I want to know does cortexm3 design kit include...
  • Is there any relationship between BOOT and REMAP in design kit?
    Hi Now I'm trying to digging the design kit. But I cant' find the BOOT relative port or signal and REMAP signal in the design kit. As I know usually BOOT used such as the following picture ...
  • What does "CMSDK_GPIO1->ALTFUNCSET = (1<<5);" do?
    Dear All, I came across initial function as the below, void UartStdOutInit(void) { CMSDK_UART2->BAUDDIV = 16; CMSDK_UART2->CTRL = 0x41; // High speed test mode, TX only CMSDK_GPIO1->ALTFUNCSET = ...
  • What does system memory work actually?
    Hi. Currently. I'm trying to understand about system memory in cortex m3 address map. most examples are said "there are 2 area such as 0x08000000 Flash memory area and 0x1FFFF000 System memory area...