• STRD ATOMIC?
    Hi, I make a software for Cortex-A9 and Cortex-M4 (both uni-processor system). Question. Is 64bit-aligned STRD(64bit memory access) atomic ? (I know tha It is not atomic, but i don't know behavior.) For...
  • Cortex M4 L1 data cache policy
    I have some confusions about the difference between write back + write allocate and write back + write no allocate on Cortex CM4. As my original understanding: For write back with write allocate...
  • Cache attribute write back/write allocate for Cortex-M4
    What is different between write back with write allocate and write with non write allocate on Cortex-M4.
  • C/C++ atomic operation on ARM9 and ARM Cortex-M4
    I have a question about C/C++ atomic operation on ARM9 and ARM Cortex-M4. I am using ARMCC compiler with C / C++ languages. It interests me if it is possible that an interrupt will be handled in the middle...
  • How to test atomic access implemented with Load Store Exclusive Assembly (LDREX / STREX)
    Hi there, i have several inline assembly functions wrapped in C. They implement atomic / read-modfy-write style Compare And Swap Increment Decrement Lock Semaphore Creating a good...