• Present program counter address
    Good day, I want to refresh and (or) update my knowledge on ARMv7. Is it true for ARMv7-M that when CPU starts execute one instruction, PC value has already been updated/is being updated in parallel...
  • ARMv7-M: Question about syn/asynchronous exception?
    Hi all, I have little experience with bare metal programming at STM32 series and currently studying exception behavior in "ARMv-7m Architecture Reference Manual" . I'm confused about syn/asynchronous...
  • Is SVC pendable on cortex-m?
    Hey. I read ARMv7-M Arch manual. SHCSR register have SVCALLPENDED bit. So that, It seem SVC is pendable. But, 'Priority escalation' is written, When the group priority of a pending synchronous...
  • Cortex-M RTOS related exceptions and concepts
    Hello, Recently, I came back to digging into RTOS working principles at the lowest level on Cortex-M family processors. I understand the concept of SysTick (or other time base), SVC and PendSV as RTOS...
  • When an exception is taken into account
    Hi Related to ARMv7-M architecture: I am searching through all infocenter documents but still cannot find anything and answer this question: "When an exception is taken into account?" I mean, are...