• Instruction Fault Generation
    Hi Experts, Is there any sample code or way to generate the Instruction Fault by forcing the processor (Cortex R). For Example, I tried below but no updates in IFSR (instruction fault status register...
  • Trustzone Address Space controller fault to secure monitor.
    Hi, I'm using a TZC380 (on an i.MX6 board from NXP) along with NXP CSU to protect some part of my DDR ram and some sensitive devices. For the TZC configuration, I choose an action set to 3: "sets...
  • Hard Faults and MemManage Faults in Cortex m3/m4
    I wrote a simple program, where I am writing to an illegal memory location. Writing in an illegal Memory location generates a MemManage fault. And if MemManage is not enabled, HardFault in generated....
  • Unhandled fault: alignment fault (0x92000061) at 0x00000000fff0f729
    Hi, I have an arm cortex A-57 machine that is running 3.16 linux kernel (64bit) compiled using gcc-linaro-aarch64_be-linux-gnu-4.9-2014.09_linux toolchain. My application (32bit) is accessing a member...
  • How to compute a cache size?
    It might be a typo in the site, infocenter.arm.com/.../index.jsp . It should be 64KB (not 32KB) based on the picture. > Index (# of lines): 2^8 > # of Words per line: 2^4 > # of Bytes per word: 2^2...