• Updated ARMv7-M architecture reference manual for Cortex-M7 ?
    Has an updated v7m architecture reference been published yet?
  • Is SVC pendable on cortex-m?
    Hey. I read ARMv7-M Arch manual. SHCSR register have SVCALLPENDED bit. So that, It seem SVC is pendable. But, 'Priority escalation' is written, When the group priority of a pending synchronous...
  • mismatch between ARMv7-M ref manual and core_cm7.h
    The ARMv7-M reference manual notes there eight ITM trace enable registers called ITM_TER0 to ITM_TER7. However, core_cm7.h only has one ITM_TER register. Can you clarify? Is it an error in core_cm7.h...
  • Is a DMB required between loading BASEPRI and storing BASEPRI_MAX?
    Hi, I have a question regarding BASEPRI, BASEPRI_MAX, and DMBs as they relate to both the V7-M and V7E-M architectures. Let's say I have the following assembly, // stuff mrs r0, BASEPRI msr BASEPRI_MAX...
  • Cortex-M RTOS related exceptions and concepts
    Hello, Recently, I came back to digging into RTOS working principles at the lowest level on Cortex-M family processors. I understand the concept of SysTick (or other time base), SVC and PendSV as RTOS...