• Clarity on EDBGRQ on CM4
    All, We are using CM4 in our design. I am looking for a way to halt the CM4 core using non-JTAG based debugger. One particular signal on CM4 that caught our attention is "EDBGRQ". From the manual...
  • Event Recorder with STM32F0
    I have been able to get the Event Recorder mostly working with ARM-MDK 5.27, in order to get debugging messages out of my STM32F0 (Cortex-M0) MCU. However, I've run into two issues that I am hoping someone...
  • ARM PMU access DRAM Event
    Hi, accorting to the reference manual of cortex A7 https://static.docs.arm.com/ddi0464/f/DDI0464.pdf pagina 243, what event number i neet to select to count all the DRAM access (read / write)?
  • Cache ECC in Cortex-R5 & Event bus
    Hi everybody, I am using a Cortex-R5 embedded in a TMS570LC4357, and I am wondering to use the cache configuration as "Do not generate Aborts, force write through, enable hardware recovery". As far...
  • Event counters take differing number of cycles
    We have some code that sets up various event counters and reads them.  We bracket this code with reads of the cycle counter.  We have noticed that depending on what event counter we are configuring, we...