• Armv8 Memory Mapping
    I am looking to emulate an Apple II and would like to specify some address ranges as being memory mapped so that any access would result in perhaps an interrupt that I am then able to handle and in which...
  • Non-Cacheable memory and DMA on armv7a
    Hi ! Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0). We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro...
  • Whether Armv7-A has a Write Buffer
    Hi, Does Armv7-A have a write buffer? If yes, when will the write buffer be drained and what's the purpose of write buffer?
  • Behavior for other data on a STR (ARMv7-A)
    When the following line is executed, what is the behavior with respect to the other words in the cache line? STR r1, [r0] The 4 bytes of data in r1 is written to the address in r0. But cache-lines...
  • Barrier after access to memory mapped register?
    Hi, Iam wondering if it makes sense to have a memory barrier after access to a memory mapped register. I looking at a driver, unfortunately not open source, that has a memory barrier after a read from...