• The exact definition of outer and inner in ARMv7
    Hello, I'm reading ARMv7 architecture reference manual and there are the following keywords: outer cacheable inner cacheable outer sharable inner sharable It looks like that outer/inner...
  • Inner/Outer Cacheability in Cortex V8-R
    I am trying to configure memory attribute for cortex R52 in our SOC which is having integrated L1 I/D Cache and no coherent agent.and having system RAM. system is having two clusters with two cores...
  • Inner/Outer share ability in Cortex R52
    I am trying to configure memory attribute for cortex R52 in our SOC which is having integrated L1 I/D Cache and no coherent agent.and having system RAM. system is having two clusters with two cores...
  • How to set inner of outer shareability on page table entry WITHOUT TEX remap??
    At first, sorry to my fool English. I want to know how to set to inner or outer shareable attribute on page table entry using TEX, C, B and  S bit (without TEX remap). I knew if i use TEX remap, the PRRR...
  • why Interrupt 1023 (Spurious interrupt) happens when i set pagetable attribute on exynos5250?
    Hi, experts. I'm developing pagetable on exynos5250 and exynos5433. But i have very strange problem.... when i mapping secure-memory-area as section with attributes that is                S = 1, TEX=...