• What will I get if I try to access SCR in cp15 when my core is in non secure mode.
    I know that when the core is in non secure mode (non TZ), the normal world software is not able to access SCR in cp15. But I'm wondering what consequence it will cause if such operations occur. Unexpected...
  • Programming TZASC in Secure Mode
    Hi everyone, I am working to setup the TZASC on I.MX6UL based dev platform platform. I did the following. - Running SPL bootloader from OCRAM - Disable the bypass (by setting GPR9's bit 0...
  • "CPSIE I"on an ARMv7A not changing the I bit in the CPSR register in USR mode - why?
    I'm using a CortexA8 and I can't seem to enable interrupts...! I'm using a "CPSIE I" instruction, I can see that the compiler (GCC) is not optimizing my code out... I have to manually stop the program...
  • ARMv7: How to set SP in secure and non secure mode ?
    Hello, I'm working on Raspberry PI2, ARMv7 and now specifically trying the secure modes. I managed to get the PI start in secure state, then here I can set the SP for all the modes I intend to use...
  • How does ARM11 respond to a non-secure interrupt in secure mode?
    Note: This was originally posted on 19th March 2009 at http://forums.arm.com Hi All, Assuming that ARM11 is running a secure process and receives a non-secure IRQ or FIQ, how does ARM11 respond to a non...