• Ignored bits in ARMv7a LPAE / ARMv8 Table descriptors
    Hi ! Let's first consider ARMv8 aarch64 VMSA and stage 1 Table descriptors. I can read in the ARM ARM in 'Next-level attributes in stage 1 VMSAv8-64 Table descriptors' that bits [58:52] are Ignored...
  • AArch64 TLB maintenance requirements
    Hello all, I want to improve VM operation in AArch64 port of FreeBSD but I stuck on following problem. The FreeBSD VM subsystem is capable to map various *kernel* objects by using superpage (higher order...
  • armv7a/armv8 : Undefined Abort Exception and MMU
    Hi ! When MMU is enabled, and a undefined abort exception is triggered, are we sure that the address stored in the `lr` / `elr_elx` registers is actually mapped by the MMU, or should I check that before...
  • Question about LPAE(Large Physical Address Extensions) for ARMv7
    I read the ARMv7 architecture reference manuals. The spec. says LPAE allows 32-bits VA to be translated into 40-bits PA. The 40-bits PA means the width of address bus is 40-bits or greater than 40 bits...
  • Non-Cacheable memory and DMA on armv7a
    Hi ! Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0). We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro...