• Barriers in in-order cores like cortex-A53, A7
    Hi experts! As you know, power efficient arm like cortexA7, A53 has in-order pipleline. However as far as I understanding, Barriers like dmb, dsb, isb are related with out-of-order memory access. But...
  • Cortex-A53 processor instruction cycles
    hi , I want to know the cycle information ,latencies of each instruction(secially vector instructions in A32 and A64) in coretex A53 architecture. It seems there is no document available which specifies...
  • [Cortex-A53] STP instruction stores out of the specified memory
    Hi Experts, I have a question about "STP" instruction in Cortex-A53. STP W6, W6, [SP, #20] --> after it executes, the memory of [sp, #16] and [sp, #28] are corrupted. I don't know why cause it....
  • Reason for Cortex A53 delays
    Hello, I want to write a bit-banging driver for a Raspberry Pi 3 (Cortex A53 with 4 cores). For testing I developed a simple Linux kernel mode driver which toggles a GPIO pin with approx. 1Mhz. In order...
  • Cortex-A53 Cache protection
    Hello all, The "Core Technical Reference Manual" specifies in chapter 8.2 the error reporting mechanism for all types of uncorrectable errors in the caches, except for L1 D-cache data (which is SEC...